Semiconductor memory device

ABSTRACT

A semiconductor memory device includes a memory cell portion and a peripheral circuit portion. The memory cell portion includes a pillar capacitor with a lower electrode, a dielectric film, and an upper electrode sequentially formed on a side surface of a first insulating portion which is parallel to a predetermined direction, and a transistor electrically connected to the lower electrode. The peripheral circuit portion includes a plate electrode, a cylinder capacitor with an upper electrode, a dielectric film, and a lower electrode sequentially formed on a side surface of the plate electrode which is parallel to the predetermined direction, and a transistor electrically connected to the lower electrode.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a division of co-pending application Ser. No.12/421,049 filed Apr. 9, 2009, which claims foreign priority to Japanesepatent application 2008-102556 filed Apr. 10, 2008. The entire contentof each of these applications is hereby expressly incorporated byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device and amethod of manufacturing the semiconductor memory device.

2. Description of the Related Art

A DRAM (Dynamic Random Access Memory) is composed of memory cells eachmade up of a transistor and a capacitor. The capacitor is composed of alower electrode, a dielectric film, and an upper electrode. In recentyears, with advanced semiconductor miniaturizing techniques, ensuring arequired area for electrodes in the DRAM has been difficult.

Thus, to increase the area for the electrodes, Japanese Patent Laid-OpenNo. 2001-217406 discloses a technique of using an inner wall and anouter wall formed like crowns as an upper electrode and a lowerelectrode, respectively, to increase capacity. FIG. 11 shows a recessedlower electrode similar to the lower electrode in Japanese PatentLaid-Open No. 2001-217406.

In FIG. 11, the lower electrode is denoted by 105. The lower electrodein FIG. 11 is formed as follows. First, a transistor and a contact plugare formed such that the contact plug is electrically connected to oneof a source region and a drain region of the transistor. Thereafter, aninterlayer insulating film is formed all over the resulting surface. Amask pattern is then formed on a portion of the interlayer insulatingfilm which is located on a region forming a memory cell portion.

Thereafter, by performing wet etching, the interlayer insulating film isremoved except for the portion of the interlayer insulating film whichis located under the mask pattern, to form an opening. A conductivematerial is then deposited on an inner wall of the opening to form alower electrode. The interlayer insulating film is then removed. At thistime, the internal surface (the interior of the recessed structure) ofthe lower electrode is exposed.

Efforts have been made to develop a method of preventing formation of astep between the memory cell portion and the peripheral circuit portion.Japanese Patent Laid-Open No. 2001-217406 and WO 97/019468 disclosemethods of reducing a step that may be formed at the boundary betweenthe memory cell portion and the peripheral circuit portion.

SUMMARY OF THE INVENTION

In one embodiment, there is provided a semiconductor memory deviceincluding a memory cell portion and a peripheral circuit portion,

wherein the memory cell portion comprises:

a first insulating portion extending in a predetermined direction;

a capacitor including a lower electrode, a dielectric film, and an upperelectrode sequentially formed on a side surface of the first insulatingportion which is parallel to the predetermined direction;

a plate electrode electrically connected to the upper electrode; and

a transistor including a source region and a drain region one of whichis electrically connected to the lower electrode, and

the peripheral circuit portion comprises:

a plate electrode extending in the same direction as the predetermineddirection;

a capacitor including an upper electrode, a dielectric film, and a lowerelectrode sequentially formed on a side surface of the plate electrodewhich is parallel to the predetermined direction; and

a transistor including a source region and a drain region one of whichis electrically connected to the lower electrode.

In another embodiment, there is provided a method of manufacturing asemiconductor memory device, the method comprising:

forming a transistor and a contact plug in a memory cell portion formingregion and a peripheral circuit portion forming region, the contact plugbeing electrically connected to one of a source region and a drainregion of the transistor;

depositing an interlayer insulating film all over the memory cellportion forming region and the peripheral circuit portion formingregion;

forming a plurality of first openings in the interlayer insulating filmin the memory cell portion forming region such that the contact plug isexposed, and forming a second opening in the interlayer insulating filmin the peripheral circuit portion forming region so as to enclose apredetermined region and to expose the contact plug;

depositing a conductive material on an inner wall of each of the firstand second openings so as to leave an opening portion unfilled, to forma lower electrode;

filling an insulating material in each of the first openings with thelower electrode formed therein, to form a first insulating portion, andfilling an insulating material into the second opening with the lowerelectrode formed therein;

removing the interlayer insulating film from the memory cell portionforming region and removing the interlayer insulating film composing thepredetermined region in the peripheral circuit portion forming region toform a third opening;

depositing a dielectric film so as to cover a surface of the lowerelectrode in the memory cell portion forming region with the dielectricfilm and to cover an inner wall of the third opening in the peripheralcircuit portion forming region with the dielectric film;

filling a conductive material, in the memory cell portion formingregion, between the first insulating portions each formed with thedielectric film and the lower electrode, to form an upper electrode, anddepositing a conductive material in the third opening so as to leave anopening portion unfilled in the peripheral circuit portion formingregion to form an upper electrode; and

forming a plate electrode in the memory cell portion forming region suchthat the plate electrode is electrically connected to the upperelectrode, and filling a conductive material into the opening portion ofthe third opening in the peripheral circuit portion forming region toform a plate electrode.

In another embodiment, there is provided a semiconductor memory devicecomprising:

a memory cell portion including a plurality of first capacitors, each ofthe first capacitors including a first lower electrode formed along afirst insulating wall, a first upper electrode, and a first dielectricfilm formed between the first lower electrode and the first upperelectrode; and

a peripheral circuit portion including at least one second capacitor,the second capacitor including a second lower electrode formed along asecond insulating wall, a second upper electrode, and a seconddielectric film formed between the second lower electrode and the secondupper electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

The above features and advantages of the present invention will be moreapparent from the following description of certain preferred embodimentstaken in conjunction with the accompanying drawings, in which:

FIG. 1 is a diagram showing a step of an example of a method ofmanufacturing a semiconductor memory device according to the presentinvention;

FIG. 2 is a diagram showing a step of the example of the method ofmanufacturing the semiconductor memory device according to the presentinvention;

FIG. 3 is a diagram showing a step of the example of the method ofmanufacturing the semiconductor memory device according to the presentinvention;

FIG. 4 is a diagram showing a step of the example of the method ofmanufacturing the semiconductor memory device according to the presentinvention;

FIG. 5 is a diagram showing a step of the example of the method ofmanufacturing the semiconductor memory device according to the presentinvention;

FIG. 6 is a diagram showing a step of the example of the method ofmanufacturing the semiconductor memory device according to the presentinvention;

FIG. 7 is a diagram showing a step of the example of the method ofmanufacturing the semiconductor memory device according to the presentinvention;

FIG. 8 is a diagram showing a step of the example of the method ofmanufacturing the semiconductor memory device according to the presentinvention;

FIG. 9 is a diagram showing a step of the example of the method ofmanufacturing the semiconductor memory device according to the presentinvention;

FIG. 10 is a diagram showing a step of the example of the method ofmanufacturing the semiconductor memory device according to the presentinvention; and

FIG. 11 is a diagram showing a related semiconductor memory device.

In the drawings, numerals have the following meanings. 1: interlayerinsulating film, 2: tungsten plug, 3: silicon nitride film, 4:interlayer insulating film, 5: photo resist, 6: capacitance pattern, 7:groove pattern, 8: capacitance pattern, 9: capacitive lower electrodeTiN film, 10: silicon nitride film, 11: photo resist, 12: memory cellportion wet cutting pattern, 13: peripheral circuit portion wet cuttingpattern, 14: peripheral circuit portion capacitive lower electrode, 15:capacitive film, 16: capacitive upper electrode, 17: capacitive plateelectrode, 18: photo resist, 19: capacitive electrode pattern, 23: firstopening, 24: second opening, 26: predetermined region, 27: thirdopening, 101: interlayer insulating film, 102: tungsten plug, 103:silicon nitride film, 104: interlayer insulating film, 105: capacitivelower electrode, 106: wet damage, 107: pattern collapse, 200: siliconsubstrate.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The invention will be now described herein with reference toillustrative embodiments. Those skilled in the art will recognize thatmany alternative embodiments can be accomplished using the teachings ofthe present invention and that the invention is not limited to theembodiments illustrated for explanatory purposes.

FIG. 10 is a diagram showing an example of a semiconductor memory deviceincluding a DRAM. FIG. 10A is a top view of a semiconductor memorydevice. FIG. 10B is a sectional view of the semiconductor memory devicetaken along direction A-A′ in FIG. 10A. The semiconductor memory devicein the present example includes a transistor electrically connected to acapacitor. However, in FIG. 10, the transistor is omitted.

As shown in FIG. 10A, the left side, in the figure, of the semiconductormemory device in the present example corresponds to a memory cellportion. The right side corresponds to a peripheral circuit portion.Dummy groove pattern 7 is formed at the boundary between the memory cellportion and the peripheral circuit portion so as to enclose the memorycell portion. Dummy groove pattern 7 forms a boundary portion.

A plurality of pillar capacitors 6 are formed in the memory cellportion. As shown in FIG. 10B, each of capacitors 6 is composed of firstinsulating portion 30 extending in predetermined direction 28, and lowerelectrode 9, dielectric film 15, and upper electrode 16 sequentiallyformed on a side surface of the first insulating portion which isparallel to predetermined direction 28, and plate electrode 17electrically connected to upper electrode 16. The first insulatingportion is shaped like a pillar. The pillar shape of the firstinsulating portion allows dielectric film 15 and upper electrode 16 tobe easily formed on the side surface thereof. The pillar shape alsoenables an increase in the contact area between the first insulatingportion and dielectric film 15.

A plurality of first insulating portions 30 each with lower electrode 9,dielectric film 15, and upper electrode 16 sequentially formed on theside surface thereof are arranged at regular intervals in particulardirection 20. A plurality of first insulating portions 30 compose arrayof first insulating portions 30. The memory cell portion has a pluralityof arrays of first insulating portions 30. The adjacent arrays arearranged such that the first insulating portions in one array arestaggered with respect to the first insulating portions in the otherarray. A conductive material is filled between the first insulatingportions each with the lower electrode and the dielectric film formed onthe side surface thereof to make up upper electrode 16. Arranging thefirst insulating portions in this manner allows the capacitors to beformed at a high density per unit area. This allows for refinement.

Furthermore, one of a source region and a drain region of a transistor(not shown in the FIGS) is electrically connected to lower electrode 9.The transistor may be a planar-type transistor or a Fin-type transistor.A semiconductor substrate 200 is formed under the lower electrode 9. Onetransistor and one capacitor make up one memory cell in a DRAM (DynamicRandom Access memory). In the DRAM, information can be stored incapacitor 6 by expressing a state in which charge is accumulated and astate in which no charge is accumulated, as two values.

The peripheral circuit portion includes at least one cylinder capacitor.FIG. 10A shows an example in which the peripheral circuit portionincludes two capacitors. Each of the capacitors includes plate electrode17 extending in the same direction as predetermined direction 28, andupper electrode 16, dielectric film 15, and lower electrode 9sequentially formed on a side surface of plate electrode 17 which isparallel to predetermined direction 28. The capacitors and transistorsin the peripheral circuit portion can be used as, for example, aminiaturized voltage compensating circuit for stabilizing voltage.

Plate electrode 17 is shaped like a rectangular parallelepiped. Therectangular parallelepipedic shape of plate electrode 17 allows theareas of upper electrode 16 and lower electrode 9 to be increased, whileensuring sufficient miniaturization. Furthermore, lower electrode 9 isformed on an inner wall of an opening formed so as to cover dielectricfilm 15. Lower electrode 9 makes up a recessed structure. A part oflower electrode 9 is in contact with dielectric film 15. Insulatingmaterial 10 is filled in the recessed structure making up the lowerelectrode. Moreover, one of the source and drain regions of thetransistor (not shown in the FIGS) is electrically connected to lowerelectrode 9. The transistor may be a planar-type transistor or aFin-type transistor. A semiconductor substrate 200 is formed under thelower electrode 9.

Boundary portion 7 is formed between the memory cell portion and theperipheral circuit portion. Boundary portion 7 includes conductivematerial film 21 formed on an inner wall of an opening extending in thesame direction as predetermined direction 28, and second insulatingportion 22 filled in the opening.

A constituent material for the first insulating portion of the memorycell portion, insulating material 10 of the peripheral circuit portion,and the second insulating portion of the boundary portion is notparticularly limited provided that the material offers an insulatingproperty. However, silicon nitride is preferably used. A constituentmaterial for upper electrode 16 and lower electrode 9 in the memory cellportion and peripheral circuit portion is not particularly limitedprovided that the material is conductive. However, TiN is preferablyused.

Thus, in the semiconductor memory device in the present example, thepillar capacitor is formed in the memory cell portion. The cylindercapacitor is formed in the peripheral circuit portion. In the memorycell portion and the peripheral circuit portion, after lower electrode 9is formed, insulating material 10 is filled inside lower electrode 9(the interior of the recessed structure). This enables problems that mayoccur during the subsequent steps to be avoided: for example, during wetetching, an etchant may permeate the inside of lower electrode 9 to etchan unexpected region. As a result, the memory cell portion and theperipheral circuit portion can be prevented from being improperlyformed.

Furthermore, the first insulating portion is present inside the lowerelectrode of the memory cell portion. Thus, the first insulating portionserves as a support to improve the strength of the lower electrode. As aresult, the lower electrode can be prevented from being collapsed.Moreover, in the peripheral circuit portion, the lower electrode, thedielectric film, and the upper electrode are sequentially formed on theside surface of the plate electrode. This enables an increase in theareas of the lower and upper electrodes, while enabling a reduction inthe area occupied by the capacitor to ensure sufficient miniaturization.

Now, with reference to FIGS. 1 to 10, an example of a method ofmanufacturing a semiconductor memory device according to the presentexemplary embodiment will be described.

First, a transistor (not shown in the FIGS) was formed in a memory cellportion forming region and a peripheral circuit portion forming region.Then, interlayer insulating film 1 was formed all over the resultingsurface. Then, as shown in FIG. 1, a semiconductor substrate wasprepared. The contact plugs 2 were formed in interlayer insulating film1 so as to be electrically connected to one of the source and drainregions of the transistor. Silicon nitride film 3 was then deposited toa thickness of 30 nm to 100 nm by an LP-CVD method. Silicon oxide film 4was deposited to a thickness of 0.5 μm to 1.5 μm as an interlayerinsulating film by a plasma CVD method. A photo resist was then formedon silicon oxide film 4. Photo resist pattern 5 was thereafter formedusing a lithography method.

Then, as shown in FIG. 2, a plasma dry etching technique was used toform a plurality of cylindrical first openings 23 in interlayerinsulating film 4 in the memory cell portion forming region throughphoto resist pattern 5 as a mask so that contact plugs 2 were exposed ininterlayer insulating film 4 in the memory cell portion forming region.At this time, the first openings were formed such that a plurality ofarrays of the first openings were arranged at regular intervals in aparticular direction and such that the first openings in one of theadjacent arrays were staggered with respect to the first openings in theother array. Simultaneously with the formation of the first openings,second opening 24 was formed in interlayer insulating film 4 in theperipheral circuit portion forming region so as to enclose rectangularparallelepipedic predetermined region 26 and to expose the contact plug.In this step, the first and second openings were formed to extend inpredetermined direction 28. Thereafter, photo resist pattern 5 wasremoved.

Then, as shown in FIG. 3, TiN film 9 was deposited all over theresulting surface to a thickness of 5 nm to 30 nm by a thermal CVDmethod using a TiCl₄ gas. At this time, TiN film 9 was formed in each ofthe first and second openings so as to leave an opening portionunfilled. Thereafter, the TiN film on interlayer insulting film 4 wasremoved by the dry etching technique to form lower electrode 9 on aninner wall of each of the first and second openings.

Then, as shown in FIG. 4, silicon nitride film 10 was deposited all overthe resulting surface to a thickness of 10 to 50 nm by the LP-CVDmethod. Silicon nitride 10 was thus buried inside the first and secondopenings. At this time, first insulating portion 30 was formed in eachof the first openings. Then, a photo resist was formed on siliconnitride film 10.

Thereafter, photo resist pattern 11 was formed using the lithographymethod so that the memory cell portion forming region had cuttingpattern 12, whereas the peripheral circuit portion forming region hadcutting pattern 13. FIG. 5A is a top view showing this condition. FIG.5B is a sectional view showing a cross section taken along directionA-A′ in FIG. 5A. FIGS. 6 to 9 also show cross sections taken along thedirection A-A′ in FIG. 5A.

As shown in FIG. 5, the cutting pattern 12 was formed in the peripheralcircuit portion forming region. In the subsequent steps, the exposedsilicon nitride 10 was etched by film thickness thereof using the photoresist pattern 11 as a mask, to form the first insulating portions 30.This etching simultaneously leaved a beam made of the silicon nitride 10connecting a plurality of capacitors 6 on upper surface of the lowerelectrode 9 in the memory cell portion forming region. As a result, thecapacitor 6 can be prevented from being collapsed when the silicon oxide4 in the memory cell portion forming region is removed in the subsequentsteps.

Then, as shown in FIG. 6, silicon nitride film 10 was removed throughphoto resist pattern 11 as a mask by the plasma dry etching method, toexpose silicon oxide film 4.

Thereafter, as shown in FIG. 7, wet etching using a diluted hydrofluoricacid was performed, which exhibits a higher etching rate for siliconoxide film 4 than for silicon nitride film 10. That is, in the memorycell portion forming region, silicon oxide film 4 was removed. In theperipheral circuit portion forming region, silicon oxide film 4 makingup predetermined region 26 was removed to form a third opening(reference numeral 27). As a result, in the memory cell portion formingregion, an outer wall of each of lower electrodes 9 was exposed. In theperipheral circuit portion forming region, the third opening enclosed bylower electrodes 9 was exposed.

Then, as shown in FIG. 8, dielectric film 15 was sequentially depositedall over the resulting surface. As a result, dielectric film 15 wasformed to cover the surfaces of the lower electrodes in the memory cellportion forming region, while covering lower electrode 9 making up aninner wall of the third opening in the peripheral circuit portionforming region. Thereafter, TiN film 16 was deposited all over theresulting surface to a thickness of 10 nm to 30 nm. At this time, in thememory cell portion forming region, TiN was filled between the firstinsulating portions each formed with dielectric film 15 and lowerelectrode 9, to form upper electrode 16. At the same time, in theperipheral circuit portion forming region, a TiN film was deposited onthe inner wall of the third opening so as to leave an opening portionunfilled, to form the upper electrode.

Thereafter, as shown in FIG. 9, tungsten film 17 was deposited all overthe resulting surface. As a result, in the memory cell portion formingregion, plate electrode 17 was formed on upper electrode 16. In theperipheral circuit portion forming region, plate electrode 17 was formedso as to fill the opening portion of predetermined region 26. Photoresist pattern 18 with a predetermined pattern was thereafter formed ontungsten film 17.

Then, as shown in FIG. 10, plasma dry etching was performed throughphoto resist pattern 18 as a mask to process plate electrode 17 andupper electrode 16 so as to prevent the communication between plateelectrode 17 and upper electrode 16, between the memory cell portionforming region and the peripheral circuit portion forming region.

Thus, the semiconductor memory device in the present example wassuccessfully formed.

It is apparent that the present invention is not limited to the aboveembodiments, but may be modified and changed without departing from thescope and spirit of the invention.

1. A device comprising: an insulating pillar that includes an uppersurface, a bottom surface and a side surface between the upper andbottom surfaces; a first conductive film including a first portionformed on the bottom surface of the insulating pillar and a secondportion continuously elongated from the first portion to cover the sidesurface of the insulating pillar; an insulating film formed on thesecond portion of the first conductive film; and a second conductivefilm formed on the insulating film; the first and second conductivefilms and the insulating film therebetween serving as first and secondelectrodes and a dielectric film therebetween of a capacitor,respectively.
 2. The device as claimed in claim 1, wherein theinsulating film is elongated over the upper surface of the insulatingpillar beyond a tip portion of the second portion to provide anelongated portion, and the second conductive film extends over theelongated portion of the insulating film.
 3. The device as claimed inclaim 1, further comprising a conductive plug selectively formed in afirst insulating layer, the first portion of the first conductive filmbeing in contact with the conductive plug.
 4. The device as claimed inclaim 3, further comprising a second insulating film formed between theinsulating film and a portion of the first insulating layer around theconductive plug.
 5. The device as claimed in claim 4, wherein theinsulating pillar is same in material with the second insulating film.6. A device comprising: an interlayer insulating layer; a plurality ofconductive plugs formed in the interlayer insulating layer apart fromone another; and a plurality of capacitors each formed in contact withan associated one of the conductive plugs; wherein each of thecapacitors comprises: a lower electrode including a bottom portion and apipe portion, the bottom portion including a first main surface and asecond main surface opposite to the first main surface, the first mainsurface being in contact with a part of the associated one of theconductive plugs, the second main surface including a first part and asecond part surrounding the first part, the pipe portion protrudingupwardly from the second part of the second main surface of the bottomportion; an insulating pillar protruding upwardly from the first part ofthe second main surface of the bottom portion of the first electrode tofill an inside of the pipe portion of the first electrode; a dielectricfilm formed on an outside surface of the pipe portion of the firstelectrode; and a second electrode formed on the dielectric film.
 7. Thedevice as claimed in claim 6, wherein the second electrodes of thecapacitors are in contact with one another to form a plate electrode. 8.The device as claimed in claim 7, wherein the insulating pillars of thecapacitors are formed separately from one another.
 9. The device asclaimed in claim 6, wherein the dielectric film of each of thecapacitors is elongated over a top portion of the insulating pillarbeyond a tip end of the pipe portion of the first electrode to form anelongated portion; and the second electrode extends to cover theelongated portion of the dielectric film.
 10. The device as claimed inclaim 9, wherein the insulating pillars of the capacitors are formedseparately from one another, and the second electrodes of the capacitorsare in contact with one another to form a plate electrode.
 11. Thedevice as claimed in claim 6, wherein the dielectric films of thecapacitors are formed continuously with one another to form a continuousdielectric film and the second electrodes of the capacitors are formedcontinuously with one another to form a plate electrode.
 12. The deviceas claimed in claim 11, further comprising an etching stopper filmformed around the bottom portions of the first electrodes of thecapacitors to intervene between the interlayer insulating layer and thecontinuous dielectric layer, the etching stopper film and the continuousdielectric layer intervening between the interlayer insulating layer andthe plate electrode.
 13. A device comprising: a substrate; an interlayerinsulating layer over the substrate; and a memory cell array comprisinga plurality of word lines, a plurality of bit lines, a plurality ofmemory cells each disposed a different one of intersections of the wordand bit lines, a plate electrode, and a plurality of conductive plugsselectively formed in the interlayer insulating layer, each of thememory cells comprising a transistor and a capacitors: wherein thetransistor of each of the memory cells comprises: a first diffusionregion connected to an associated one of the bit lines, a seconddiffusion region connected to an associated one of the conductive plugs,and a gate electrode connected an associated one of the word lines; andwherein the capacitor of each of the memory cells comprises: aninsulating pillar extending vertically, a lower electrode including afirst portion sandwiched between the insulating pillar and an associatedone of the conductive plugs in contact with the insulating pillar andthe associated one of the conductive plugs, and a second portionelongated from the first portion vertically along the insulating pillar,and a dielectric film formed between the second portion of the lowerelectrode and the plate electrode.
 14. The device as claimed in claim13, wherein the first and second portions of the lower electrodecooperate with each other to continuously surround a substantial wholeof a side surface of the insulating pillar with keeping a top portion ofthe insulating pillar uncovered.
 15. The device as claimed in claim 14,wherein the dielectric films of the capacitors are formed continuouslywith one another to cover the top portion of the insulating pillar ofeach of the capacitors.
 16. The device as claimed in claim 15, furthercomprising an insulating film formed on portions of the interlayerinsulating layer among the first portions of the first electrodes of thecapacitors to intervene between the dielectric film and the portions ofthe interlayer insulating layer.
 17. The device as claimed in claim 16,wherein the insulating film is same in material with the insulatingpillar.
 18. The device as claimed in claim 17, wherein the insulatingfilm comprises a silicon nitride film and the insulating pillar alsocomprises a silicon nitride film.